RISC-V

Extracted Attributes

• Type

  Instruction Set Architecture (ISA)

• License

  Free and open-source (Permissive)

• Member Count

  4,500+ members (as of 2025)

• Shipped Chips

  Over 10 billion cores shipped by end of 2022

• Inception Date

  2010-05-18

• Managing Organization

  RISC-V International

• Originating Institution

  University of California, Berkeley

• Managing Organization HQ

  Switzerland

Timeline

• RISC-V development officially began at the University of California, Berkeley. (Source: undefined)

  2010-05-18

• Development and maintenance of the ISA standard was transferred to RISC-V International. (Source: undefined)

  2015

• More than 10 billion chips containing RISC-V cores were reported shipped worldwide. (Source: undefined)

  2022-12-31

• RISC-V International expanded its membership to over 4,500 members. (Source: undefined)

  2025

RISC-V

RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981. In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025. RISC-V is a popular architecture for microcontrollers and embedded systems, with development of higher-performance implementations targeting mobile, desktop, and server markets ongoing. The ISA is supported by several major Linux distributions, and companies such as SiFive, Andes Technology, SpacemiT, Synopsys, Alibaba (DAMO Academy), StarFive, Espressif Systems, and Raspberry Pi offer commercial systems on a chip (SoCs) and microcontrollers (MCUs) that incorporate one or more RISC-V compatible processor cores.

Web Search Results

• RISC-V - Wikipedia

  RISC-V (pronounced "risk-five"): 1 is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981. In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025. [...] The plan was to aid both academic and industrial users. David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC, and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects at the University of California, Berkeley (RISC-I and RISC-II published in 1981 by Patterson, who refers to the SOAR architecture from 1984 as "RISC-III" and the SPUR architecture from 1988 as "RISC-IV"). At this stage, students provided initial software, simulations, and CPU designs. [...] RISC-V was begun with a goal to make a practical ISA that was open-sourced, usable academically, and deployable in any hardware or software design without royalties.: 1 Also, justifying rationales for each design decision of the project are explained, at least in broad terms. The RISC-V authors are academics who have substantial experience in computer design, and the RISC-V ISA is a direct development from a series of academic computer-design projects, especially Berkeley RISC. RISC-V was originated in part to aid all such projects.: 1

• What Is RISC-V? | Wind River

  RISC-V is an open source instruction set architecture (ISA). It is designed to be simple, modular, and extensible, providing a foundation for building a wide range of processors and systems. RISC-V offers a set of instructions that define the operations a processor can perform, the formats of those instructions, and the architectural features of the system. It was developed at the University of California, Berkeley, in 2010 and has gained significant attention and adoption worldwide. RISC-V follows the principles of a reduced instruction set computer (RISC), which means it aims to keep the instruction set simple and streamlined. This simplicity allows easier decoding and execution of instructions, resulting in faster and more efficient processing. [...] RISC-V works by defining a set of instructions, their formats, and the architectural features of a processor. These instructions represent the operations that a processor can perform, such as arithmetic and logical operations, memory access, branching, and more. The RISC-V ISA specifies the binary encoding for each instruction, allowing the processor to interpret and execute them. [...] The execution of RISC-V instructions follows a fetch-decode-execute cycle. First, the processor fetches an instruction from memory, using the program counter (PC) to determine the address. Then it decodes the instruction, determining the operation to be performed and any operands involved. Finally, the processor executes the instruction by performing the necessary calculations or actions. This cycle continues, sequentially fetching and executing instructions, until the program completes. RISC-V processors can be implemented using various hardware designs, such as microcontrollers, embedded systems, and high-performance processors. They can also be emulated or simulated using software tools, allowing testing and development without physical hardware.

• RISC-V: What it is and Why it Matters | Center for Security and Emerging Technology

  RISC-V is an open-source ISA managed by a Swiss standards development body (RISC-V International). Chip design teams can access and implement the RISC-V standard free of charge, avoiding costly licensing fees they would otherwise pay to Intel or Arm. Companies around the world—including American and Chinese firms—are taking advantage of RISC-V to design chips of varying complexity from simple microcontrollers to complex systems-on-a-chip. RISC-V is a particularly attractive option for Chinese chip designers as they look for ways to reduce their reliance on foreign semiconductor technology. However, given that the recent export controls are focused on AI chips (which typically use in-house ISAs), it’s not immediately obvious how a general computing ISA like RISC-V could hinder U.S. export [...] #### What is RISC-V? At the foundation of every processor’s design is a technical specification known as an instruction set architecture (ISA). The ISA describes how software will control the processor’s hardware. Specialized AI chips—for example those designed by AMD and NVIDIA—typically rely on an in-house ISA. For general computing (i.e. CPUs), however, rather than reinvent the wheel, chip design teams typically license an existing ISA from Intel or Arm (a British company). For example, for their respective CPU designs, AMD licenses from Intel and Apple licenses from Arm. Increasingly, rather than licensing an ISA from Intel or Arm, CPU design shops are considering a third ISA option: RISC-V.

• What is RISC-V? – How Does it Work? | Synopsys

  ## Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications. Originally developed at the University of California, Berkeley, the RISC-V ISA is considered the fifth generation of processors built on the concept of the reduced instruction set computer (RISC). Due to its openness and its technical merits, it has become very popular in recent years. The standard is now managed by RISC-V International, which has more than 3,000 members and which reported that more than 10 billion chips containing RISC-V cores had shipped by the end of 2022. Many implementations of RISC-V are available, both as open-source cores and as commercial IP products. [...] The royalty-free RISC-V ISA features a small core set of instructions upon which all the design’s software runs. Its optional extensions allow designers to tailor the architecture for a variety of different end markets. Essentially, the RISC-V architecture allows designers to customize and build their processor in a way that’s tailored to their target end applications, so they can optimize the power, performance, and area (PPA) for those applications. The RISC-V ISA also provides the flexibility to pick and choose from available features, rather than having to use the full feature set. While the initial market adoption of RISC-V has been with embedded applications and microcontrollers, the open-source architecture also holds promise for high-performance computing and data centers. [...] ##### Search Synopsys ##### Popular Content Multiphysics Fusion Technology for Multi-Die Designs Explained Automotive Executive Guide: Rethinking Automotive Development Mastering AI Chip Complexity Our Technology, Your Innovation™. Trusted industry leader. ## Multiphysics Fusion Technology for Multi-Die Designs Explained Unified multiphysics fusion helps multi-die teams validate earlier and sign off faster. # What is RISC-V? ## Definition ## RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers. ##

• The RISC-V Instruction Set Manual Volume I

  Preface | Page 9 The RISC-V Instruction Set Manual Volume I | © RISC-V Chapter 1. Introduction RISC-V (pronounced "risk-five") is a new instruction-set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will also become a standard free and open architecture for industry implementations. Our goals in defining RISC-V include: • A completely open ISA that is freely available to academia and industry. • A real ISA suitable for direct native hardware implementation, not just simulation or binary translation. [...]  The name RISC-V was chosen to represent the fifth major RISC ISA design from UC Berkeley (RISC-I (Patterson & Séquin, 1981), RISC-II (Katevenis et al., 1983), SOAR (Ungar et al., 1984), and SPUR (Lee et al., 1989) were the first four). We also pun on the use of the Roman numeral "V" to signify "variations" and "vectors", as support for a range of architecture research, including various data-parallel accelerators, is an explicit goal of the ISA design. The RISC-V ISA is defined avoiding implementation details as much as possible (although commentary is included on implementation-driven decisions) and should be read as the software-visible interface to a wide variety of implementations rather than as the design of a particular hardware artifact. The RISC-V manual is structured in two

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• Instance Of

  Q170584

• Inception Date

  5/18/2010